The present invention relates to automated digital test systems. More particularly, the invention relates to a apparatus and method for driving a test sequence through a digital circuit and retrieving the outputs from selected nodes of the circuit.
Automated test equipment for digital circuits, such as integrated circuits mounted on a circuit board, generally offers high speed testing at a significant cost. Referring to FIG. 1, a schematic diagram of a conventional automatic tester 10 for testing a digital circuit is shown. Conventionally, each node of the digital circuit being tested is referred to as a channel. For each channel, electronics are provided including a shift register 12 and a driver 14. The shift registers are capable of acting at high speed and of accepting an entire sequence of drive commands for its respective channel. The drivers 14 are made up of discrete transistors. The transistor drivers 14 are capable of producing a drive signal at any of a variety of logic levels to accommodate the various different types of digital circuits that might be tested by the equipment. The outputs from each node of the digital circuit being tested are provided to a set of comparators 16. Typically, each channel is connected to a pair of comparators 16 for comparison with a high threshold and with a low threshold. The outputs from a comparator are fed serially into a shift register 18. The input shift registers 12 work at high speed to input the drive commands for operating the drivers 14 in quick succession and the output shift registers 18 receive the outputs from the comparators 16 in the same sequential manner. At the completion of the tests, the output shift registers 18 can be unloaded so that the results can be compared to the expected test pattern results. A pass-fail decision can then be made for the tested circuit. The method of this conventional high speed tester begins with a processor loading the input shift registers 12 with a drive command sequence from the memory. The drive command sequence corresponds to a series of tests to be applied to the digital circuit being tested. Each shift register 12 receives the commands for its respective channel. The contents of the shift registers 12 are clocked out to the drivers 14. As the drivers 14 are running the test sequence through the digital circuit, the outputs of the comparators are clocked into the output shift registers. The output shift registers are loaded into the processor for comparison with the expected test result pattern.
U.S. Pat. No. 4,972,413 (Littlebury et al.) suggests an alternate test equipment arrangement in which one set of shift registers is used for both the drive commands and the outputs from the comparators. Littlebury et al. includes, in its testing electronics for each channel, a bidirectional latch for filling and retrieving data from a node memory and interacting with the shift register. Also, a multiplexor is inserted between the shift register and the drivers and another multiplexor between the shift register and the comparators. The multiplexors are used to select between a scan path through which data is transferred into or out of the testing circuit and the associated driver or comparator.